6.205 Final Project by Laker and Hanfei
- Write an assembly-style program (e.g.,
matrix-mult.txt
) - Convert into machine code using
python isa.py <program_name.txt>
- Update the program file in BRAM initialization in
hdl/controller.sv
- Update the instruction count parameter when initializating
controller.sv
- Run testbench
sim/top_level_tb.sv
or real dealhdl/top_level.sv
- Update the comment in the enum for ISA in
controller.sv
- Possibly add a case statement in
controller.sv
, or updatememory_valid_for_memory_out
if it's a memory command - Possibly add a case statement in
memory.sv
if it's a memory command - Update
isa.py
to conform to the new arguments you use (return as below, and add tostr_to_command
dictionary)
return (op_code << 28) + (reg_a << 24) + (immediate << 8) + (reg_b << 4) + (reg_c << 0)
- Run
isa.py data/matrix-mult.txt
, theniverilog -g2012 -o sim.out sim/top_level_tb.sv hdl/...
, thenvvp sim.out
, thenopen dump.vcd
in GTKWave and verify that the output of the matrix multiplication remains correct (\BRAM[5][95:0] in GTKWave takes on value 0x00000000001600320013002B)